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GigE Vision FPGA Core Xilinx

GigE Core Evaluation Board In machine vision components, especially cameras, the standard GigE Vision® is now established. This standard specifies an UDP based messaging protocol to transfer data, messages and events. This could be the image data of a camera that are sent to a PC and command or configuration data that are sent to a camera device.

Sensor to Image offers a set of FPGA IP cores to fasten up design of GigE Vision® compliant machine vision devices, e.g. cameras , but also receiving components like GigE framegrabbers.

At the moment as 1GBit sender=camera and 1GBit receiver=frame grabber the Xilinx FPGA families Spartan3x, Spartan6, Virtex4, Virtex5 and Virtex6 are supported.

The design is done as well for for 10 Gigabit on VIRTEX6 FPGA and Link Aggregation on all XILINX FPGA families and will support 7series components as well as soon as they are available.

To get an easy access to this design solution, Sensor to Image provides a Spartan3E based evaluation-kit for sending and receiving applications. In addition following Xilinx boards are supported:

  • Spartan3ADSP-1800 Starter Kit
  • ML505/ML507 (Virtex5)
  • SP605 (Spartan6)
  • ML605 (Virtex6)

For further information press here...