In machine vision components, especially cameras, the standard CoaXPress® has almost established. This standard specifies an high speed protocol and direct interface to data acquisition devices. The protocol supports transfer of data, messages and events. This could be the image data of a camera that are sent to a PC frame grabber and command or configuration data that are sent to a camera device. All communication and device power is transmitted over a single 75Ohm coaxial cable, which is widely used for PAL/NTSC cameras at transfer speeds of up to 6.125GBit/cable.
Sensor to Image offers a set of FPGA IP cores to fasten up design of CoaXPress® compliant machine vision devices, e.g. cameras , but also receiving components like GigE framegrabbers.
At the moment the Xilinx FPGA families ® and Virtex6® are supported.
The design on Spartan6 FPGA works with the FPGA internal GTP 1.25GBit/200m to 3.12Gbit/100m cable length. The design on Virtex6 can run up to 6.125GBit/50m cable length.
To get an easy access to this design solution, Sensor to Image provides an FMC Addon Board, which could be used on standard XILINX evaluation boards to test sending and receiving applications.
Reference designs exist for following boards:
- Spartan6® SP605, DEVICE and HOST, 1lane CXP3
- ARTIX7® AC701, DEVICE and HOST, up to 2lane CXP6
- Kintex7® KC705, DEVICE and HOST, up to 4lane CXP6
- ZYNQ® ZC706, DEVICE and HOST, up to 4lane CXP6